Memory elements, such as D flip-flops (DFF), are subject to upset from radiation elements, such as cosmic neutrons and terrestrial alpha particles. The failure rate associated with these upsets is commonly known as a Soft Error Rate (SER), and the industrial metric used to quantify the SER of the circuit is known as a Failure In Time (FIT) rate or FIT/Mb. Master/Slave dual-interlocked storage cell (DICE) Single-Event Upset (SEU) flip-flops (FF) are designed to reduce the SER of a DFF following energetic particles irradiation.
In a typical field programmable gate array (FPGA) design having a Master-Slave flip-flop, the clock is most likely in a ‘0’ state, i.e. the Slave is in a latch mode. Therefore, converting a Slave portion of a Master/Slave memory device to DICE while keeping the Master portion as typical D-latch would reduce the overall FF FIT rate while minimizing area and performance penalty.
However, this implementation results in the Master D-latch having unbalanced load between the two storage nodes, which causes a switching frequency difference for ‘0-1’ and ‘1-0’ transitions.
Accordingly, there is a need for a memory cell that improves the FIT rate.